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Design consideration for efficient network interface supporting the Large Receive Offload with embedded RISC
Conference paper

Design consideration for efficient network interface supporting the Large Receive Offload with embedded RISC

M. Elbeshti, M. Dixon and T. Koziniec
2013 36th International Conference on Telecommunications and Signal Processing (TSP), pp.282-289
IEEE
36th International Conference on Telecommunications and Signal processing (TSP) (Rome, Italy, 02/07/2013–04/07/2013)
2013
DOI: https://doi.org/10.1109/TSP.2013.6613937
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Abstract

The Ethernet speed has increased to 40–100 Gbps since the release of IEEE P802.3ba. In this paper, we have extended the Intel's Large Receive Offload Linux software driver function to process the UDP/IP packets and to manage the out-of-order packets as well as design a scalable programmable Network Interface-based RISC core to support these functions in the Network Interface. The processing methodology and cycle processing of UDP packets inside the Network Interface are also discussed. Besides, the three-pipeline RISC's performance and data movements for high communication rates up to 100 Gbps have been measured too. The results presented herein show that an 800 MHz cost-effective embedded processor core can provide the required efficiency of the network interface to support a wide range of transmission line speeds, up to 100 Gbps. Furthermore, we have found several techniques that can contribute to packet processing and work with fewer headers and data transferring in a network interface.

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